On December 6, Broadcom announced the launch of the industry's first 3.5D F2F packaging technology, the 3.5D XDSiP platform. This advanced platform integrates over 6000mm² of silicon chips and up to 12 HBM memory stacks within a single package, addressing the high-performance, low-power requirements of large AI chips.
The 3.5D XDSiP, beyond the 2.5D packaging, connects the top metal layers of two chip layers directly, utilizing 3D hybrid copper bonding, offering minimal electrical interference and exceptional mechanical strength. This "Face-to-Face" connection provides seven times the signal density compared to traditional "Face-to-Back" vertical stacking, significantly reducing latency between components in a 3D chip stack. This innovation also cuts PHY interface power consumption by 90% and enables smaller intermediate layers and package sizes, reducing costs and mitigating warping issues in large-area packages.
Frank Ostojic, Broadcom's Senior VP and General Manager of the ASIC Products Division, stated that advanced packaging is critical for next-generation XPU clusters as the industry approaches the limits of Moore's Law. Broadcom developed the 3.5D XDSiP platform in collaboration with TSMC and EDA partners, enabling chip designers to pair each component with the appropriate manufacturing process, thus significantly enhancing performance, efficiency, and cost.
TSMC's Senior VP and Global Business Development GM, Zhang Xiaoqiang, mentioned that TSMC and Broadcom have closely collaborated to combine TSMC's advanced logic processes and 3D chip stacking technology with Broadcom's design expertise. This collaboration aims to productize the platform to drive AI innovation and future growth.
Broadcom confirmed that most of its "consumer-grade AI customers" have adopted the 3.5D XDSiP platform, with six products already in development, set to ship in February 2026. Fujitsu has also confirmed that it will use this platform in its 2nm ARM server processor, FUJITSU-MONAKA.
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