Improve the dynamic performance of broadband ADC by about 10 dBFS immediately through spurious IP suppression

     Teledyne e2v announced that it will launch EV12AQ600/5 option with integrated license key, which can directly use the new ADX4 post-processing algorithm developed by SP Devices of Teledyne Group. The ADX4 spurious suppression IP can dynamically suppress spurious frequency components caused by gain, offset and phase mismatches between the four ADC cores. Time interleaving is a reliable architecture method to improve ADC sampling rate. However, in applications above 10 bit resolution and broadband, it is very challenging to avoid spectral distortion through calibration.

     For the EV12AQ600/5, the time interleaving of the four cores increases the sampling rate from 1.6 to 6.4 GS/s. The mismatch error between ADC cores reduces the spurious free performance. The ADX4 provides spurious free dynamic range (SFDR) improvement of up to 10 dB. This improvement is particularly evident in broadband applications, as it does not require hardware design changes. Users can easily burn the ADX4 code module into the post-processing FPGA, or even at the work site.