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Infineon introduces OptiMOS source base 25 V power MOSFETs

Aug 5 2020 2020-08 Power Infineon Technologies
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Infineon Technologies AG achieves system innovation and component level improvement by focusing on solving current power management design challenges. "Source base" is a new packaging concept in line with industry standards. Infineon has introduced the first power MOSFETs based on this package concept, which are OptiMOSTM 25 V power MOSFETs in PQFN 3.3x3.3 mm package.

     Infineon Technologies AG achieves system innovation and component level improvement by focusing on solving current power management design challenges. "Source base" is a new packaging concept in line with industry standards. Infineon has introduced the first power MOSFETs based on this package concept, which are OptiMOSTM 25 V power MOSFETs in PQFN 3.3x3.3 mm package. The device sets a new industry benchmark in MOSFET performance, with not only on-state resistance (RDS(on)) reduction, but also industry-leading thermal performance metrics. The product is suitable for a wide range of applications, including motor drives, SMPS (including servers, telecommunications and OR-ing) and battery management.

 

     The new packaging concept connects the source (rather than the traditional drain) to the thermal pad. In addition to enabling new PCB layouts, this also helps achieve higher power density and performance. The two models currently launched take up different plate areas, they are: PQFN 3.3x3.3mm package with source bottom and standard gate layout; And PQFN 3.3x3.3mm package with source base and gate pole in center. The sourced-bottom, standard gate layout package is based on the current PQFN 3.3x3.3mm pin distribution layout.

 

     The position of the electrical connection remains the same, facilitating the simple and straightforward replacement of today's standard drain base package with the new source base package. In a gate-centered package, the gate pin is moved to the center position to facilitate multiple MOSFETs in parallel. Due to the increased drain-source creepage distance, the gates of multiple devices can be connected to the same PCB layer. In addition, moving the gate interface to the center also increases the source area, thereby improving the electrical connection of the device.

 

     This technological innovation enables a significant reduction in RDS(on) compared to existing technology, up to 30%. The junction to shell thermal resistance (RthJC) is also significantly improved compared to the existing PQFN package. Due to reduced parasitic effects, improved PCB losses, and excellent thermal performance, the new packaging concept can bring great added value to any contemporary engineering design.

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