Infineon introduces PQFN packaged source-base power mosFEts

     The design of future power electronics systems will continue to advance to achieve the highest level of performance and power density. In response to this trend, Infineon Technologies has introduced a new 3.3 x 3.3 mm2 PQFN package with a source base power MOSFET in the voltage range of 25-150 V and available in bottom cooling (BSC) and double-sided cooling (DSC) configurations.

     The new product family delivers significant performance improvements at the semiconductor device level, offers an attractive solution for DC-DC power conversion, and opens up new possibilities for system innovation in server, communications, OR-ing, battery protection, power tools, and charger applications.

     The new product family uses Infineon's latest MOSFET product technology and leading packaging technology to bring system performance to new levels. Inside the source base (SD) package, the source contacts of the MOSFET wafer are flipped and oriented toward the plantar side of the package, then welded to the PCB. In addition, the package has an improved drain copper clip design inside the top of the chip, achieving a market-leading chip/package area ratio.

     As the size of the system continues to shrink, the two key factors of reducing power loss and improving heat dissipation become critical. Infineon's new line of products offers a 25% reduction in on-going resistance (RDS(on) compared to the current market leader PQFN 3.3x 3.3mm ² drain-bottom package. Infineon Double-sided heat dissipation, PQFN package, OptiMOS™ source base power mosFeTs provide an enhanced thermal interface that conducts power losses from switching devices to radiators. The double-sided cooling structure can connect the power switch to the heat sink in the most direct way, and its power consumption capacity is three times higher than that of the bottom-cooling, bottom-source power MOSFET.

     The new product family offers two different pin arrangement forms, providing great flexibility for PCB wiring. The pin arrangement of traditional standard gate layout can be used to modify the existing drain base design quickly and simply. The pin arrangement of gate centered layout provides a new possibility for multiple devices to be connected in parallel, and can minimize the line distance between the driver chip and gate. The new generation 25-150 V OptiMOS™ source bottom-power mosFeTs in PQFN 3.3x 3.3mm ² package deliver superior continuous current capability up to 298A for the highest system performance.