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Infineon launched HYPERRAM memory chip, which can double the bandwidth of high-performance low pin count solution

Oct 10 2022 2022-10 Semiconductors Infineon Technologies
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Infineon Technologies Inc. has introduced a new HYPERRAM 3.0 device that further complements its high-bandwidth, low-pin memory solution. The device features a new 16-bit extended HyperBus interface that doubles throughput to 800MBps. With the introduction of the HYPERRAM™ 3.0 device, Infineon offers a complete portfolio of low-pin, low-power high-bandwidth memory products

     Infineon Technology Co., Ltd. introduced a new HYPERRAM 3.0 device to further improve its high bandwidth, low pin count memory solution. The device has a new 16 bit extended HyperBus  Interface, which can double the throughput to 800MBps. Introducing HYPERRAM  After 3.0 devices, Infineon can provide a complete high bandwidth memory product portfolio with low pin count and low power consumption. The chip is very suitable for applications that need to expand RAM memory, including video buffering, factory automation, artificial intelligence Internet of Things (AIoT) and the Internet of Vehicles (V2X), and applications that need pad memory for data intensive computing.

 

     Ramesh Chettuvetty, Senior Marketing and Application Director of Infineon Automotive Electronics Business Unit, said: "Infineon has a profound professional accumulation in the field of memory solutions for nearly 30 years, and we are very happy to bring another industry first product to the market. The data throughput of each pin of the new HYPERRAM 3.0 memory solution is much higher than that of existing technologies on the market, such as PSRAM, SDR DRAM, etc. Its low power consumption feature can achieve lower power consumption without sacrificing throughput, so this memory is an industrial and Internet of Things solution The ideal solution. "

 

     Infineon HYPERRAM is an independent volatile memory based on PSRAM, which can provide an economical and practical way to expand memory. Its data rate is equivalent to SDR DRAM, but it uses fewer pins and has lower power consumption. The data throughput of each pin of the HyperBus interface is higher, so that a microcontroller (MCU) with fewer pins and a PCB with fewer layers can be used to provide a design scheme with lower complexity and more optimized cost for the target application.

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