Microchip introduces Serial memory controllers for high-performance data center computing

     Microchip announced its entry into the memory infrastructure market with the industry's first commercial serial memory controller, expanding its data center portfolio. The SMC 1000 8 x 25G enables cpus and other compute-centric SOCs to use quadruple memory channels connected in parallel with DDR4 DRAM in the same package size. Microchip's serial memory controllers not only provide higher memory bandwidth and media independence for compute-intensive platforms, but also feature ultra-low latency.

     As the number of CPU processing cores increases, the average memory bandwidth available per processing core decreases due to the inability of CPU and SoC devices to scale the number of parallel DDR interfaces on a single chip to meet the needs of the growing number of cores. The SMC 1000 8 x 25G connects to the CPU via an 8-bit Open Memory Interface (OMI) compliant 25 Gbps channel and to memory via a 72-bit DDR4 3200 interface, dramatically reducing the number of host CPU or SoC pins required per DDR4 memory channel. Allows more memory channels and increases the available memory bandwidth.

     An OMI-enabled CPU or SoC can use a large number of media types with different cost, power, and performance metrics without the need to integrate a separate memory controller for each type. In contrast, current CPU and SoC memory interfaces are typically locked to a specific DDR interface protocol, such as DDR4, at a specific interface rate. The SMC 1000 8 x 25G is the first memory infrastructure product in Microchip's product family to support a media-independent OMI interface.

     Data center application workloads require OmI-based DDIMM memory products to provide the same high performance bandwidth and low latency effects as today's parallel DDR-based memory products. Microchip's SMC 1000 8 x 25G features an innovative low-latency design with latency increments of less than 4 ns compared to traditional LRDIMM-based integrated DDR controllers, indicating that the bandwidth and latency performance of the OmiUM-based DDIMM product is nearly identical to that of similar LRDIMM products.

     "Microchip is excited to bring to market the industry's first serial memory controller product," said Pete Hazen, vice president of Microchip's Data Center Solutions business unit. New memory interface technologies, such as the Open Memory Interface (OMI), enable a large number of SoC applications to support the growing storage needs of high-performance data center applications. Microchip's entry into the memory infrastructure market underscores our commitment to improving data center performance and efficiency."

     Steve Fields, Chief architect, IBM Power Systems, said: "IBM customers' workloads have seen a surge in storage demand, so we made a strategic decision for the POWER processor memory interface to leverage the OMI standard interface to increase memory bandwidth. IBM is pleased to partner with Microchip to deliver this solution."

     SMART Modular, Micron and Samsung Electronics are developing multi-pin efficient 84-pin differential dual-in-line memory modules (DDIMMs) with capacities ranging from 16 GB to 256 GB, conforming to the DDIMM package of the JEDEC DDR5 draft standard. These DDIMMs will feature the SMC 1000 8 x 25G and will seamlessly plug into any OMI compliant 25 Gbps interface.

     Myron Slota, President of the OpenCAPI Consortium, said: "The Open Memory Interface (OMI) standard provides a highly pin-efficient serial memory interface, so that a large number of CPU and SoC applications can scale memory bandwidth and seamlessly transition between a growing number of emerging media types, such as storage hierarchical memory. The OpenCAPI Alliance provides the host and destination IP for free and will initiate a number of measures simultaneously to ensure compliance with the standards."

     "Google customers can benefit from data-intensive applications, such as machine learning and data analytics that require high-performance memory," said Rob Sprinkle, Platform infrastructure Technology lead at Google LLC. Google strongly supports initiatives based on open standards, such as the Open Memory Interface (OMI), which provide high performance memory interfaces to meet important performance goals such as bandwidth and latency."