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Microchip introduces four new 20-way differential clock buffers

Jan 6 2020 2020-01 Power Microchip Technology
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Microchip announced the launch of four new 20-way differential clock buffers for next-generation data center applications that go well beyond the PCIe 5th Generation (Gen 5) buffering standard. The new ZL40292 (terminal resistance 85Ω) and ZL40293 (terminal resistance 100Ω) are designed specifically according to the latest DB2000Q specification, while ZL40294 (terminal resistance 85Ω) and ZL40295 (terminal resistance 100Ω) are designed according to the DB2000QL industry standard.

     As data centers migrate to higher bandwidth and faster infrastructures, the need for higher performance timing devices becomes critical. Microchip Technology introduces four new 20-way differential clock buffers for next-generation data center applications that far exceed the PCIe 5th Generation (Gen 5) buffering standard. The new ZL40292 (terminal resistance 85Ω) and ZL40293 (terminal resistance 100Ω) are designed specifically according to the latest DB2000Q specification, while ZL40294 (terminal resistance 85Ω) and ZL40295 (terminal resistance 100Ω) are designed according to the DB2000QL industry standard. All new products can be used for next-generation servers, data centers, storage devices, and other PCIe applications, and meet the specifications of PCIe 1, 2, 3, and 4 generations.

 

     Each buffer is an ideal complement to a chipset, where multiple peripheral components in data center servers and storage devices, such as central processing units (cpus), field programmable gate arrays (FPgas), and physical layers (PHYs), as well as many other PCIe applications require distributed clocks. The buffer has a low additional jitter of about 20 femtoseconds (~20 fs), far exceeding the DB2000Q/QL specification of 80 femtoseconds (80 fs), giving designers a lot of room to increase data processing rates while meeting tight timing budgets. When the clock is allocated to up to 20 outputs, the above devices can achieve ultra-low jitter, ensuring the integrity and quality of the buffer clock signal.

 

     The new clock buffer achieves low power consumption through low power High Speed Current Steering Logic (LP-HCSL), which will significantly reduce the budget in terms of power consumption. Compared to standard High Speed Current Steering Logic (HCSL), the LP-HCSL saves one-third of power consumption and significantly reduces power consumption. This performance enables customers to achieve longer lines on the board, improving signal paths, while reducing components and saving board space. ZL40292, for example, eliminates up to 80 terminal resistors (an average of 4 per path) compared to traditional HCSL buffers.

 

     Rami Kanama, vice president of Timing and Communications at Microchip, said: "Microchip offers the industry's widest range of clock and timing products and has been committed to developing high-standard solutions for next-generation networking applications such as faster data centers and enterprise infrastructure. "Microchip's previous introduction of superior performance PCIe 5th generation devices gives engineers more design room to focus on their designs, helping customers looking for DB2000Q and DB2000QL compliant clock buffers to quickly start the design process."

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