New IAR Embedded Workbench for RISC-V support Andes CoDense™ extension

     IAR Systems, a global leader in Embedded development software and services, has announced that the latest version of IAR Embedded Workbench for RISC-V version 3.11 now fully supports AndeStar™ from Andes Technology CoDense™ extensions for V5 RISC-V processors. CoDense™ is a patented extension to processor ISA (Instruction Set Architecture) that helps IAR's toolchain generate compact code to save flash memory on target processors, while AndeStar™ V5 DSP/SIMD and performance extensions implemented in previous releases help provide higher application performance. IAR Systems pioneered adaptation support shortly after the launch of AndesCore™ RISC-V CPU IP to provide customers with a complete development tool chain, Includes a powerful IAR C/C++ compiler ™ and a full debugger (also available in ISO 26262 compliant feature safety certified versions).

     Jingxin Technology is one of the founding members of RISC-V International and a leading provider of IP solutions for high performance/low power 32/64-bit embedded processors. The joint launch of Jingxin and IAR Systems solutions and their robust approach to secure application design will help customers accelerate development, including the certification process, to accelerate their time to market. The CoDense™ extension newly added to AndeStar™ V5 is the code volume compression feature that Andes has extended based on the extensible RISC-V standard instructions. This extended capability has been proven in over 10 billion SOCs using AndeStar™ V3 processors.

     In addition to its support for CoDense™, The latest 3.11 version of IAR Embedded Workbench for RISC-V will also support 0.9.11 (the standard extension for Packed-SIMD directives) with the "P" extension as well as enhanced SMP (symmetric multiprocessing) and AMP (asymmetric multiprocessing) multi-core debugging. In addition, developers are sure to love the new IAR Build and IAR C-SPY Debug extensions developed specifically for Visual Studio Code to make it easy for them to take advantage of IAR Systems' powerful tools, Build and debug their Code in the Visual Studio Code editor.

     The proven IAR Embedded Workbench is well known among RISC-V developers for its best-in-class code volume optimization capabilities, designed to help businesses use smaller chips or add more functionality to existing platforms. Because the code is generated using advanced optimization techniques from the toolchain, it has demonstrated convincingly fast code and industry-leading performance in CoreMark testing by EEMBC Certified Laboratories.

     The included C-SPY debugger gives developers full real-time control over the application, including the use of complex breakpoints, Profiling, code coverage, timelines with breaks, and power logging. Fully integrated code analysis tools ensure that code conforms to specific standards, such as MISRA C (2004 and 2012), as well as best programming practices, such as the CWE and CERT C secure coding standards. In addition, there is a functional security development certified version of IAR Embedded Workbench for RISC-V with safety reports and safety guidelines for ten different standards, such as automotive or industrial applications.

     "We are excited to offer IAR Systems full support for AndeStar™ V5 RISC-V processors, in particular the enhancements to the patented CoDense™ extension," said Dr. Charlie Su, President and Chief Technology Officer of Crystal Core Technologies. CoDense™ is popular for MCU or IoT applications because it has significantly increased code density by double digits. We expect the combination of the IAR Embedded Workbench and the AndeStar™ V5 RISC-V extension to provide up to a 30% performance increase for the RISC-V community."

     Anders Holmberg, Chief Technology Officer, IAR Systems, said: "Thanks to our close collaboration with Crystal Core Technology, we have early support for AndeStar™ V5 DSP/SIMD and performance extensions, and now fully support Andes CoDense™ for code volume compression on top of RISC-V C extensions. Striking a balance between code size and performance can significantly improve the total ROI of a product or project. With CoDense™ 's support, we will empower users to help them achieve this balance."