Renesas Electronics announces new advances in on-chip SRAM

     Renesas Electronics announces its successful on-chip development of a new dual-port static random access memory (SRAM) - in-vehicle infotainment system-on-chip (SoC) of 16 nanometers (nm) and posterity. The new SRAM is optimized for use as an automotive infotainment system chip in the video buffer memory to enable real-time image processing capabilities required for future autonomous vehicle technologies. When testing the new SRAM in a state-of-the-art 16 nm process, it achieved two 688 picoseconds (PS) of 0.7 volts at low voltage conditions and an industry-leading high integrated density of 3.6 megabits per square millimeter at high speed.

     In-vehicle infotainment systems, such as automotive navigation systems and Advanced Driver assistance systems (ADAS), have made significant progress in preparing the autonomous vehicles of the future. In these systems, real-time image processing technology is critical to the realization of autonomous vehicles, and is limited by only increasing the integration density with finer feature sizes and using higher clock frequencies to improve this real-time processing capability.

     To address these limitations, there has also been an effort to further improve performance by using split images to convert into smaller parts and processing individual pieces of parallel algorithms. Dual-port on-chip SRAM is now expected to work with these algorithms because it can perform read and write operations while achieving about twice the performance of standard single-port on-chip SRAM. Compared to single-port SRAM, however, this two-port SRAM has several problems, including not only the need for more chip area to be affected, but also increased power consumption, when the access speed is increased, worse lower voltage tolerance and other issues.

     Renesas has successfully addressed these issues by adopting dual port SRAM storage units optimized for FinFET devices. The company also applied a word line booster type auxiliary single-port SRAM to achieve high-speed read and write operations that are stable at lower voltages and allow for a small power consumption chip area to inhibit the development of circuit technologies.