
Renesas Electronics announced a partnership with Andes Technology Startup Technology IP, a leading provider of RISC-V architecture embedded CPU cores and related SoC development environments. Renesas has selected AndesCoreTM 32-bit RISC-V CPU core IP for use in its new dedicated standard product and will begin offering samples to customers in the second half of 2021.
Frankwell Lin, President of Andes Technology, said: "We are proud that Renesas, a top MCU supplier, has designed the Andes RISC-V kernel into its pre-programmed, purpose-built standard product. Renesas and Andes share the same vision - to embrace RISC-V as the dominant CPU instruction set architecture (ISA) for system-on-chip (SoC). The collaboration is not only a milestone for Andes, but also a sign that the open source RISC-V ISA is on its way to becoming a mainstream computing engine. Renesas customers will also benefit from a modern ISA built for 21st century computing needs."
Sailesh Chittipeddi, Executive Vice President, iot and Infrastructure Business Unit General Manager, Renesas Electronics, said: "The scalable performance range, optional security features and customization options offered by the Andes RISC-V core IP enable Renesas to provide innovative solutions for future standard products for specific applications. Help customers looking for cost-effective alternatives to existing or emerging applications benefit from shorter time to market and lower development costs."
Renesas' pre-programmed ASSP devices based on the RISC-V core architecture, combined with dedicated user interface tools to set the programmable parameters of the application, will provide customers with a complete and optimized solution. This capability removes barriers associated with RISC-V early development and software investment. In addition, Renesas' extensive regional partners have a wealth of expertise and will provide customers with cutting-edge, dedicated technical support.
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