Research progress of 3D interconnect technology and heterogeneous integration of chips

     With the continuous improvement of chip integration, today's chip size has become smaller and smaller, and the integrated functions on the chip are more and more complex. This brings great challenges to the chip design, how to achieve more functions in a limited space, how to improve the performance and reliability of the chip, has become the focus of attention. In order to solve these problems, in recent years, the research of three-dimensional chip interconnection technology and heterogeneous integration has been widely concerned and in-depth research.

     The technology of three-dimensional chip interconnection refers to the vertical stacking of different layers of chips through copper column, silicon mud mat and packaging technology, so as to realize the interconnection and signal transmission between chips. Compared with traditional 2D interconnection technology, 3D interconnection technology has the advantages of higher integration, shorter signal transmission distance and lower power consumption. At the same time, three-dimensional interconnect technology can also achieve heterogeneous integration, that is, different chips, devices or materials are integrated on the same chip, so as to achieve richer functions and higher performance.

     In the aspect of chip 3D interconnection technology, the main research content includes vertical interconnection technology, packaging technology, thermal management technology and so on. Among them, vertical interconnection technology is one of the key technologies, which can realize the interconnection and signal transmission between different layers of chips. The current vertical interconnect technology mainly includes Through-Silicon Via (TSV) and Through-Glass Via (TGV). TSV technology uses silicon mud mat to connect chip layer through vertical copper column to realize signal transmission between chips. The TGV technology uses a glass mud mat to connect the chip layer through a vertical glass column. Compared with TSV technology, TGV technology has higher signal transmission speed and lower loss.

     Packaging technology is another important direction, which mainly studies how to package stacked chips into a whole. The current packaging technology mainly includes ball grid array package (BGA), shot grid array package (LGA) and so on. Packaging technology can not only protect the chip, but also realize the signal transmission and power management between the chips.

     Thermal management technology is also an important problem to be solved in 3D interconnect technology. Because of the higher integration density of three-dimensional stacked chips, heat emission is also more difficult. Therefore, how to achieve efficient thermal management and heat dissipation has become one of the problems to be solved in 3D interconnection technology.

     In addition to chip 3D interconnection technology, heterogeneous integration is also one of the focuses of current research. Heterogeneous integration refers to the integration of different types of chips, devices or materials on the same chip to achieve more functionality and higher performance. At present, the main research contents of heterogeneous integration include silicon-based heterogeneous integration, hybrid integration, power integration and so on.

     Silicon-based heterogeneous integration is mainly to integrate different types of silicon-based chips together, such as CMOS chips and optoelectronic devices, so as to achieve optoelectronic integration; Hybrid integration is to integrate different types of chips or devices together, such as CMOS chips and MEMS devices, so as to achieve smart sensors and other applications; Power integration is the integration of power devices in the same chip to achieve efficient power management.

     In general, chip three-dimensional interconnection technology and heterogeneous integration are the important direction of the development of chip technology today, they can achieve higher integration, more rich functions and higher performance. With the continuous development and improvement of technology, it is believed that three-dimensional interconnect technology and heterogeneous integration will play an increasingly important role in future chip applications.