Silicon Labs introduces a complete portfolio of clock solutions that meet the latest generation of PCIe 5.0 specifications

     Silicon Labs has introduced a complete portfolio of clock solutions that meet the latest generation PCI Express® (PCIe®) 5.0 specification, providing best-in-class jitter performance with significant design margin. The Si5332 Arbitrary Frequency Clock family produces PCIe Gen 5 reference clocks with jitter performance up to 140fs RMS, optimizing PCIe SerDes performance while meeting the Gen 5 specification with margin. The Si5332 clock is capable of generating any combination of PCIe and universal frequencies, enabling clock tree integration in a variety of applications

     Silicon Labs also offers the Si522xx PCIe clock generator and Si532xx PCIe buffer series, which are capable of providing 2, 4, 8 or 12-way PCIe Gen 1/2/4/4/5 compatible outputs and are ideal for a wide range of PCIe endpoint clocks in data center applications.

     Data center hardware designs, including network interface cards (nics), PCIe bus extenders, and high-performance computing (HPC) accelerators, increasingly use low-power 1.5V or 1.8V power supplies to minimize overall power consumption. The Si522xx and Si532xx devices are powered by a 1.5-1.8 V power supply and are the lowest power consumption PCIe clocks and buffers in the industry. The Si522xx and Si532xx output drivers utilize Silicon Labs' proven push-pull high-speed current Steering logic (HCSL) technology, eliminating the need for external terminal resistance required by traditional PCIe clocks with constant current output driver technology.

     Silicon Labs' new clock products are fully compatible with PCIe Gen 5 Universal Clock, Separated Reference No Spread Frequency (SRNS) and Separated Reference Independent spread Frequency (SRIS) architectures. Although PCIe Gen 5 has more stringent jitter requirements, Silicon Labs' new product does not require a discrete power filter component, which simplifies PCB layout while ensuring that board-level noise does not degrade clock jitter performance. Board designers can seamlessly upgrade existing PCIe Gen 1/2/3/4 designs, easily implemented using pin-compatible Si5332, Si522xx, and Si532xx clocks to take advantage of faster PCIe serial interfaces.

     James Wilson, General Manager of Clock Products at Silicon Labs, said: "Silicon Labs is committed to providing best-in-class clock solutions for easy migration to higher speed PCI Express. Data center designers want to leverage PCIe Gen 5 to increase the speed of the interconnect between cpus and workload accelerators, including Gpus, FPgas, and dedicated accelerator solutions. Increasing bandwidth for network, storage and AI resources will help the industry transition to 400G Ethernet."