Silicon expands the Si539x jitter attenuator family

     Silicon Labs has expanded the Si539x jitter attenuator family with a new device model that features a fully integrated reference clock, enhances system reliability and performance, and simplifies PCB layout in high-speed network designs. The new Si539x jitter attenuator is designed to meet the demanding reference clock requirements in 100/200/400/600/800G designs, providing more than 40% margin for the rigorous jitter requirements required for 56G PAM-4 SerDes in state-of-the-art Ethernet switch SOCs, PHYS, FPgas, and ASics. It also provides future solutions for emerging 112G SerDes designs.

     James Wilson, general manager of Clock products at Silicon Labs, said: "Network equipment vendors are racing to develop faster, higher-capacity devices that can handle 5G wireless traffic. This shift is driving the demand for higher performance clock solutions in fronthaul/backhaul, metro/core, and data center applications. Fpgas and PHYs integrated with 56 Gbps SerDes support higher capacity 100/200/400/600/800G fiber and Ethernet card, but face the challenge of increasingly complex board design and layout. "By integrating a reference clock in Silicon Labs' latest Si539x jitter attenuator, we are making it easier for the industry to migrate to higher port count, higher capacity 100/200/400/600/800G designs."

     Improved system reliability and performance - The new Si539x jitter attenuator incorporates a highly reliable crystal that has been thoroughly tested over the full temperature range and pre-screened for activity dip. The Si539x device has fully passed a variety of reliability tests, including shock, vibration, temperature cycling and crystal aging. The well-regulated crystals and innovative device architecture reduce the sensitivity of the crystals to temperature changes caused by the system's fans, resulting in more consistent and reliable operation.

     High audio emission noise immunity - Device structures with integrated reference clocks have higher audio emission (AE) immunity than external crystal designs. AE is the noise wave radiation that occurs when a PCB is subjected to a temperature gradient or external mechanical force that causes microcracks or plastic deformation in the PCB assembly. Unlike discrete crystals, which have greater frequency errors due to AE, the innovative package structure of the Si539x device isolates and protects the crystal from AE noise, ensuring reliable operation and consistent frequency response.

     Save board area - Customers designing high-end optical fiber and Ethernet cable cards place great emphasis on reducing the overall board area. By using a jitter attenuator with an integrated reference clock, developers can reduce the PCB footprint by more than 35%, with an added benefit: The integrated reference clock eliminates the need for a no-cloth zone below the crystal, so more dense clock routing can be done around the device, further simplifying the PCB layout.

     Frequency flexibility and clock distribution - The Si539x device can generate any combination of 100 Hz to 1028 MHz frequencies on up to 12 differential clock outputs, eliminating the need for commonly used stand-alone clock generators and clock buffers. These advantages enable a "clock tree on chip" clock while eliminating the additional jitter associated with discrete clock tree solutions.