Start by providing a fully customizable RISC-V IP kernel for large amounts of data

     Semdynamics has released the world's first fully customizable 64-bit RISC-V kernel family, perfect for handling large amounts of data for applications including AI, ML, and HPC. These cores are process-independent and are currently offered in versions as low as 5nm. Roger Espasa, CEO and founder of semiddynamics, explains, "Until now, the configuration of RISC-V processor cores was either fixed by the vendor or had very limited configurable options such as cache size, address bus size, interface, and a few other control parameters. Our new IP core gives customers complete control over configuration, whether it's new instructions, separate address Spaces, new memory access capabilities, etc. This means that we can tailor a core precisely to meet the needs of each project, so that there are no unnecessary overhead or compromises. More importantly, we can implement the client's "secret weapon" functionality into RTL in a matter of weeks, which no one else can provide. Every designer using RISC-V expects perfect power consumption, performance and area, as well as unique differentiating features, and now, for the first time, they can get that from us."

     The first in this family to now offer licensing is atrevideo Core. This provides out-of-order scheduling in combination with the company's proprietary Gazzillion technology, so it can handle highly sparse data with long delays and the high-bandwidth memory systems typical of current machine learning applications. In effect, the Gazzillion technology eliminates the latency problems that can occur when using CXL technology to provide remote memory in order to have the high-speed access it provided when it was developed. For demanding workloads such as high performance computing (HPC), the atrevideo kernel supports large memory capacities for both 64-bit local data paths and 48-bit physical address paths.

     Espasa added, "We have the fastest core in the market that can move large amounts of data across each clock's cache line even when the data is not suitable for caching. We can do this at the 2.4GHz frequency of the right node. Other companies in the market on average have a cache line every many, many cycles, which is nowhere near as much as we have a cache line every cycle. So if the application streams a lot of data and/or the application hits very large data that is not suitable for caching, we have the best RISC-V kernel on the market." With its full MMU support, atrevideo also supports linux, including support for cache consistent, multiprocessing environments ranging from two to hundreds of kernels. It is already vector ready, with support for RISC-V vector specification 1.0 and the upcoming semi-dynamic open vector interface.

     Vector instructions intensively encode a large number of calculations to reduce the amount of energy used by each operation. The Vector Gather directive effectively supports sparse tensor weights to assist ML workloads. He concluded, "We've been in stealth mode as we've created the core architecture that the RISC-V community really wants -- an architecture with full customizability, not just a few adjustable Settings. No one else has such a complex RISC-V core that can be fully configured to perfectly meet the specific needs of each project without having to use off-the-shelf cores and compromises."