Teledyne SP Devices Announces 12-Bit Digitizer with 7 GB/s Sustained Data Rate

     Teledyne SP Devices, a business unit of Teledyne Technologies, has released the ADQ32 and ADQ33, fourth-generation modular data acquisition boards optimized for high-throughput applications. With the combination of an onboard open field programmable gate array (FPGA) and high-speed data streaming, the ADQ32 and ADQ33 are ideal for even the most computationally demanding applications.

     The ADQ32 dual-channel 12-bit digitizer supports simultaneous sampling at 2.5 Gb/s per channel, while the ADQ33 supports simultaneous sampling at 1 GS/s per channel and features an open Xilinx Kintex Ultrascale KU040 field programmable gate array (FPGA). Both digitizers are optimized for high-volume applications and are therefore suitable for original equipment manufacturers (OEMs) in scanning source optical coherence tomography (SS-OCT), time-of-flight mass spectrometry (ToF-MS) and distributed fiber optic sensing ( DOFS) and other fields for integration. The ADQ33 is not subject to export controls, so no license is required.

     Users can execute custom dedicated digital signal processing (DSP) in real-time in the on-board FPGA to characterize signals and extract valuable information. It can also be used to perform data reduction so that the output rate matches the 7 G/s sustained transfer capacity of the PCI Express interface. The data can then be post-processed on the central processing unit (CPU) of the host PC, or transferred peer-to-peer to the graphics processing unit (GPU).

     This architecture provides great flexibility, allowing the designer to use the most appropriate type of processing resource in the delegated tasks. Examples of dedicated DSPs include Fast Fourier Transform (FFT) and k-space remapping for SS-OCT, and waveform averaging and zero suppression for ToF MS.

     In addition to high flow rates and computational flexibility, the ADQ32 offers excellent analog performance including effective number of bits (ENOB), spurious free dynamic range (SFDR), and more. Hardware triggering, internal/external clock selection, and general-purpose input/output (GPIO) simplify system-level integration.