The 5-output ultra-low jitter clock splitter with PLL provides a unique multi-chip output synchronization method

     Linear Technology Corporation introduces the LTC6950, a low-phase noise integer N synthesizer core with an ultra-low jitter clock distribution output circuit. The LTC6950 is ideal for generating and distributing low-jitter signals essential for high signal-to-noise ratio (SNR) clock data converters. When digitizing or synthesizing high analog frequencies, keeping the data converter clock jitter low is fundamental to achieving excellent SNR levels. For example, new electronic systems require direct digitizing of RF and high IF signals with ADCs. With 18fsRMS jitter (at 12kHz to 20MHz bandwidths), the LTC6950 guarantees the best performance for this type of system.

     The LTC6950 uses Linear Technology's proprietary EZSyncTM output synchronization method, which simply and efficiently synchronizes multiple outputs from one chip or multiple chips along the edge. EZSync synchronizes the rising edge by determining a common CMOS input with loose timing requirements. In addition, EZSync synchronization can be used to produce repeatable and determinable phase relationships between the clock divider outputs of those devices with this feature enabled.

     The phase-locked loop (PLL) inside the LTC6950 stands out because it has a -226 DBC /Hz normalized in-band phase noise layer (or quality factor) and an unusually low -274 DBC /Hz normalized 1/f phase noise that remains intact through the clock division portion. These specifications ensure that designers can take advantage of the good phase noise performance of external oscillators locked by the LTC6950 and provide the best jitter performance in this class of devices.

     To simplify the design process for the LTC6950, Linear Technology offers the ClockWizardTM simulation and design tool free of charge. When using the ClockWizard GUI, loop filter component values can be found at the click of a button, and the tool also accurately predicts the phase noise and jitter of a single output, helping designers make the right choices during the design and debugging phases.