Ti's CDCDB400 DB800ZL buffer is designed for use with PCIe Gen 1 through 6, QPI, UPI, SAS, and SATA reference clocks in CC, SRNS, or SRIS architectures

     The Texas Instruments CDCDB400 is a four-output LP-HCSL, and the db800zl is compatible with a clock buffer with low attached jitter and low propagation latency. The buffer can meet the strict performance requirements of PCIe Gen 1 to Gen 6, QPI, UPI, SAS, and SATA interfaces in CC, SRNS, or SRIS architectures. CDCDB400 allows buffering and copying of a clock source with up to four separate outputs in LP-HCSL format. The device also includes status and control registers that can be accessed through an interface compliant with SMBus version 2.0.

     The clock buffer integrates external passive components to reduce overall system costs. CDCDB400 meets or exceeds the system parameters in the DB800ZL and DB2000Q specifications. The device is available in 5 mm x 5 mm, 32 pin VQFN package.