Xilinx launches HLx version of Vivado design Kit

     Xilinx announced the HLx version of the Vivado design Suite, which offers a new approach to ultra-productive design for All Programmable SoCs and FPGas and for building reusable platforms. The new HLx includes the HL System version, HL Design version, and HL WebPACK™ version. All HLx releases include Vivado High-Level Synthesis (HLS) with C/C++ libraries, Vivado IP Integrator (IPI), LogicCORE IP subsystem, and the complete Vivado implementation tool suite. Make it easy for mainstream users to adopt the most productive and advanced C language and IP design process. Combined with the latest UltraFast™ Advanced Productivity Design methodology guide, users can increase productivity 10-15 times compared to traditional methods. The new HLx version will be available as a free upgrade to the Vivado design suite.

     Over the past three years, Xilinx's cutting-edge customers have pioneered the adoption of C - and IP-based design technologies and methods, and pushed them to maturity, and these mature technologies and methods are now incorporated into HLx versions, which are proven to increase productivity by 10-15 times. In order to achieve this ultra-high productivity, the customer adopts all or part of the following design technologies and methods: 1) Design and optimization reuse based on C language; 2) Reuse of IP subsystem; 3) Integrated automation; 4) Accelerate design convergence.

     Unlike traditional RTL designs, which devote most of their design effort to the back end of the design process, C - and IP-based designs can support a wide range of optimized design reuse to accelerate the creation of better micro-architectures and quickly explore more design possibilities, and can replace error-prone manual C-to-RTL transformations. Avoid wasted time and errors when integrating C-based and RTL-based IP, and significantly reduce validation time. With high-level abstractions, customers find that they can quickly achieve the same or better overall quality of results (performance, power, and utilization).

     To support these highly productive design processes, all new HLx releases include Vivado HLS, Vivado IPI, LogicCORE IP subsystems, and a complete suite of Vivado implementation tools. In addition, Xilinx and its alliance ecosystem continue to expand market-specific C libraries, such as OpenCV for video and image processing, and machine learning for automotive driver assistance systems (ADAS) and data center applications. Xilinx's new LogiCORE IP subsystem is a highly configurable, market-specific building block that integrates up to 80 different IP cores, software drivers, design paradigms and multiple test platforms. The new IP subsystem can be used for Ethernet, PCIe, video processing, image sensor processing, and OTN development. These IP subsystems use industry standards such as the AMBA AXI 4 interconnection protocol, IEEE P1735 encryption, and IP-XACT to interoperate and accelerate integration with IP from Xilinx and its alliance members.

     The combination of C-based IP and pre-packaged IP subsystems enables integration automation with Vivado IPI. Vivado IPI's integrated automation provides an interactive development environment with device and platform awareness. The environment supports intelligent automatic connectivity of critical IP interfaces, one-click IP subsystem generation, real-time DRC, and interface change notifications, while also providing powerful debugging capabilities. Platform-aware intelligence preconfigures Zynq SoC and MPSoC processing systems with appropriate peripherals, drivers, and memory maps to support the target development board. Design teams can now quickly identify, reuse, and integrate hardware and software IP cores for ARM processing systems and high-performance FPGA logic.

     Tom Feist, Senior Director of Marketing, Xilinx Design Methodology, said: "The new HLx release design suite provides the architecture for creating and programming a reusable All Programmable platform. All of our Vivado kits offer advanced tools, IP and UltraFast design methods that allow our mainstream customers to focus on differentiated value and create better designs faster."