
Xilinx has officially launched the Virtex UltraScale+ VU19P, the world's largest FPGA. It is reported that the VU19P uses a 16nm process, based on the Arm architecture, with 35 billion transistors, that is, the highest logic density and the largest number of I/ OS ever in a single chip, and can support the simulation and prototyping of the most advanced ASIC and SoC technologies in the future. VU19P will also support a wide range of test and measurement, computing, networking, aerospace and defense related applications.
The role of the FPGA chip is to simulate and prototype the cutting-edge chip before it flows, that is, the chip that exists for the manufacture of chips, is the chip for the chip manufacturer. Under the background of continuous progress of chip manufacturing process and increasingly complex manufacturing process, chip designers have extremely high initial investment costs, and the use of FPGA chips can reduce costs, reduce the risk of chip flow, improve efficiency and accelerate the process of product market.
The VU19P has 9 million system logic units, DDR4 memory bandwidth of up to 1.5 Terabit per second, transceiver bandwidth of up to 4.5 Terabit per second, and more than 2,000 user I/ OS. It makes it possible to create prototypes and simulations of today's most complex SOCs, while also supporting a variety of complex emerging algorithms, such as those used in artificial intelligence (AI), machine learning (ML), video processing, and sensor fusion. Compared to the previous generation of the industry's largest capacity FPGA (UltraScale 440 FPGA at 20 nm), the VU19P increases capacity by 1.6 times.
It is understood that VU19P is the third generation of Xilinx to refresh the world record FPGA, before the first generation of Virtex-7 2000T, the second generation of Virtex UltraScale VU440, and VU19P in addition to providing hardware technology, but also for developers to provide hardware and software collaboration verification. Enable them to start software and customization before they even get their hands on a physical device, and collaborate to optimize the design process with the Xylinx Vivado design suite.
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