Xilinx releases SDSoC development environment for fully programmable SoCs and MPsoCs

Xilinx announced the launch of SDSoC development environments for fully programmable SoCs and MPsoCs. As the third member of Xilinx's SDx family of development environments, the SDSoC development environment enables the broader community of systems and software developers to benefit from the powerful benefits of "fully programmable" SoCs and MPSoC devices. The SDSoC environment provides a greatly simplified ASSP-like programming experience, including an easy-to-use Eclipse Integrated Design Environment (IDE) and a comprehensive development platform for heterogeneous Zynq fully programmable SoCs and MPSoC deployments. SDSoC, combined with the industry's first C/C++ system-wide optimization compiler, provides system-level characterization, automatic software acceleration with programmable logic, automatic system connection generation, and libraries to speed up programming efforts. In addition, it helps end users and third-party platform developers quickly define, integrate, and validate system-level solutions, and supports end customers with custom programming environments.

Assp-like programming experience

Systems and embedded software engineers adopt SDSoC and can use C/C++ running on bare metal or operating systems such as Linux and FreeRTOS as input to the Eclipse IDE. SDSoC enables the creation of complete heterogeneous multiprocessing systems, including the reuse of traditional HDL IP modules as libraries for available C language calls. Unlike traditional, separate hardware - and software-centric processes that can lead to development delays and uncertainty in system architecture and performance, SDSoC is carefully architected-to provide rapid system characterization, software acceleration with programmable logic, and system architecture exploration within a familiar framework.

Full system optimized compiler

SDSoC provides a system-optimized compiler for ARM processors and programmable logic. SDSoC enables software teams to quickly configure and generate macro/micro architectures through automated system connection generation, providing optimal system connectivity and memory interfaces, and enabling rapid system exploration of performance, throughput, and latency with shorter design iterations. The compiler uses the basic high-level integrated compiler technology currently used by more than 1,000 programmers. In addition, SDSoC offers optional hardware optimization libraries from Celinx and Auviz Systems, a member of the Celinx Alliance, that enable high-performance, low-power acceleration of programmable logic.

Description of system-level features

SDSoC can quickly estimate system performance based on the advanced software system description feature of the current Xilinx SDK, which measures hardware and software performance of complete designs running on the Zynq platform. With fast system performance estimation, users can determine which functions should be accelerated with programmable logic, and SDSoC can use C/C++ code to report software cycles and estimate data transfer and overall application acceleration, which can quickly generate and explore the best overall system performance and power consumption early.

Expert usage model for platform developers

SDSoC provides board support packages (BSPS) for Zynq fully programmable SoC development boards (such as ZC702, ZC706, etc.) as well as third-party and market-specific platforms (such as Zedboard, MicroZed, ZYBO, and video image development kits). The metadata contained in the BSP helps software developers and system architects abstract platform details, simplifying the creation, integration, and validation of heterogeneous, smarter systems. Using platforms provided by Xilinx or created by customers, SDSoC enables truly software-configurable smarter systems.

Davor Kovacec, founder and CEO of Xylon, said: "Using Xilinx's new SDSoC development environment, combined with the MicroZed development board vision platform for embedded graphics video and XylonlogicBRICKS™IP, non-traditional FPGA developers can now quickly configure complete intelligent vision systems through familiar C/C++ workflows. And the prototype design and development. This combination will truly unlock the power and potential of both fully programmable SoCs and MPsoCs for all design teams."